An optimized harmonic elimination method based on synchronized microcontroller architecture

Authors: VIVEK GOPINATH, MEENU NAIR, JAYANTA BISWAS, MUKTI BARAI

Abstract: This paper proposes an optimized synchronous PWM method for harmonic elimination in a quasi square wave inverter. The synchronized PWM method enables online harmonic computation and PWM pulse generation in a multitasking digital controller to eliminate lower order harmonics. The multitasking digital controller reduces the look-up table requirement and helps in realizing efficient implementation to eliminate dominant harmonics. This method offers a simple scalable solution for combined fifth and seventh harmonic elimination using two low-cost eight-bit PIC microcontrollers (PIC18F4550, PIC18F452). Experimental results are demonstrated for a single-phase three-level inverter. The proposed method achieves 90$\% $ reduction of fifth and seventh harmonic components from a quasi square wave inverter output.

Keywords: Pulse width modulation, synchronized architecture, harmonic elimination, fast Fourier transform

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