FPGA implementation of a low-power and area-efficient state-table-based compression algorithm for DSLR cameras

Authors: MOHD RAFI LONE, NAJEEB UD DIN HAKIM

Abstract: Small image acquisition devices like digital single lens reflex (DSLR) cameras most commonly use Joint Photographic Expects Group (JPEG) coding standard for lossy compression. Although JPEG is a simple coding standard, its compression efficiency is very low as compared to any typical state-of-the-art image coding standards like set partitioning in hierarchical trees (SPIHT). In this paper, a novel state-table-based SPIHT (STS) algorithm and its field programmable gate array (FPGA) implementation is proposed. The STS uses two small state-tables and two extremely small lists. The STS not only provides better compression efficiency than the state-of-the-art JPEG 2000 at high bit rates but also requires very small memory to hold the state-tables and lists in comparison to SPIHT. On average STS requires 0.86\% of the memory needed by SPIHT when evaluated for image sizes ranging from 4 Mpixels to 40 Mpixels. The implementation results show that STS consumes very less FPGA area in comparison to SPIHT-based architectures. The dynamic power dissipation of STS is also less than that of JPEG-like compression standards. This makes our proposed algorithm a better candidate for compression in low-power, low-memory digital image acquisition devices.

Keywords: Set partitioning in hierarchical trees, very large-scale integration, image compression, dynamic power dissipation, field programmable logic array, digital single lens reflex

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