Implementation of zero voltage switched SEPIC/ZETA bidirectional converter for low power applications using FPGA

Authors: VENMATHI MAHENDRAN, RAMAPRABHA RAMABADRAN

Abstract: This paper presents a derived SEPIC/ZETA bidirectional converter (BDC) with reduced ripple in the noninverted output voltage. This converter is obtained by the fusion of unidirectional SEPIC and ZETA converters that ensures reduced ripple in the inductor currents. The optimal selection of duty ratio enables the proposed converter to operate either in SEPIC or ZETA mode under forward and reverse power flow. The presence of auxiliary circuit not only reduces the voltage stress on the switches by operating under zero voltage switching condition but also provides isolation between the input and the output ports. The operational principle and the stability of the proposed SEPIC/ZETA BDC have been analyzed under different modes of operation. To validate the performance of the proposed converter, the implementation is carried out using a field programmable gate array (FPGA)-based digital controlled prototype model.

Keywords: Bidirectional power flow, SEPIC/ZETA bidirectional converter, pulse width modulation, stability analysis, zero voltage switching

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