Dual bit control low-power dynamic content addressable memory design for IoTapplications

Authors: V V SATYANARAYANA SATTI, SRIDEVI SRIADIBHATLA

Abstract: The Internet of things (IoT) is an emerging area in the semiconductor industry for low-power and high-speedapplications. Many search engines of IoT applications require low power consumption and high-speed content addressablememory (CAM) devices for the transmission of data packets between servers and end devices. A CAM is a hardwaredevice used for transfer of packets in a network router with high speed at the cost of power consumption. In this paper,a new dual bit control precharge free (PF) dynamic content addressable memory (DCAM) has been introduced. Theproposed design uses a new charge control circuitry, which is used to control the dual DCAM cell to get the match lineoutput for match/miss. Elimination of the precharge phase before the evaluation phase allows the proposed design toperform more search operations within the evaluation time. The proposed 64-bit PF-DCAM design is implemented usinga CMOS 45-nm technology node and Monte Carlo simulations are performed for power and search delay validation. Thesimulation results show that the proposed design reduces power and search delay when compared to conventional DCAMdesigns.

Keywords: Dynamic content addressable memory, IoT, low power, match line, search delay

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